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asahi kasei [ak4352] m0040-e-02 2000/11 - 1 - general description the ak4352 is an 18bit low voltage & power stereo dac for digital audio system. the ak4352 uses the new developed multi-bit ds architecture, this new architecture achieves dr=94db at low voltage operation. the ak4352 includes post filter with single-ended output and does not need any external parts. the ak4352 is suitable for the portable audio system like md, etc as low power and small package. features multi-bit ds dac sampling rate ranging: 8khz ~ 50khz on chip post filter on chip buffer with single-ended output on chip perfect filtering 8 times fir interpolator passband: 20khz passband ripple: 0.06db stopband attenuation: 43db digital audio i/f format: 2s compliment, msb first 18bit msb justified, 16/18bit lsb justified, i 2 s digital de-emphasis for 44.1khz sampling master clock: 256fs or 384fs thd+n: -83db@2v, -89db@3v d-range: 94db@2v, 96db@3v output voltage: 1.10vpp@2v low voltage operation: 2v (1.8 ~ 3.6v) low power dissipation: 6mw@2v very small package: 16pin tssop lrck bick sdata serial input interfac e vdd vss vcml dif1 dif0 pd vref cks clock divider mclk dem de-emphasis control vcmr aoutl aoutr ds modulator 8x interpolator ds modulator 8x interpolator lpf lpf 2v & low power multi-bit ds dac ak435 2 www.datasheet.co.kr datasheet pdf - http://www..net/
asahi kasei [ak4352] m0040-e-02 2000/11 - 2 - n ordering guide ak4352vt -40 ~ +85 c 16pin tssop (0.65mm pitch) akd4352 evaluation board n pin layout 1 mclk pd sdata bick dif0 dif1 dem top view 2 3 4 5 6 7 8 cks vcml aoutr aoutl vcmr vref vdd vss 16 15 14 13 12 11 10 9 lrck pin/function no. pin name i/o function 1 mclk i master clock pin 2pd i power-down pin when at l, the ak4352 is in power-down mode and is held in reset. the ak4352 should always be reset upon power-up. 3 bick i serial bit input clock pin this clock is used to latch audio data. 4 sdata i audio data input pin 5 lrck i l/r clock pin this input determines which audio channel is currently being input on sdata pin. 6 7 dif0 dif1 i i digital input format pin these pins select one of four input modes. 8 dem i de-emphasis enable pin when at h, de-emphasis of fs=44.1khz is enabled. 9 vss - ground pin 10 vdd - power supply pin 11 vref i reference voltage input pin normally connected to vdd. 12 vcmr o rch common voltage pin 13 aoutr o rch analog output pin 14 aoutl o lch analog output pin 15 vcml o lch common voltage pin 16 cks i master clock select pin l: 256fs h: 384fs note: all input pins should not be left floating. www.datasheet.co.kr datasheet pdf - http://www..net/
asahi kasei [ak4352] m0040-e-02 2000/11 - 3 - absolute maximum ratings (vss=0v;note 1) parameter symbol min max units power supply vdd -0.3 4.6 v input current, any pin except supplies iin - 10 ma input voltage vind -0.3 vdd+0.3 v ambient operating temperature ta -40 85 c storage temperature tstg -65 150 c note 1. all voltages with respect to ground. warning: operation at or beyond these limits may results in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (vss=0v;note 1) parameter symbol min typ max units power supply vdd 1.8 2.0 3.6 v voltage reference (note 2) vref - vdd v note 1. all voltages with respect to ground. note 2. analog output voltage scales with the voltage of vref. aout (typ.@0db)=1.10vpp*vref/2. *akm assumes no responsibility for the usage beyond the conditions in this data sheet. www.datasheet.co.kr datasheet pdf - http://www..net/
asahi kasei [ak4352] m0040-e-02 2000/11 - 4 - analog characteristics (ta=25 c; vdd=2.0v, vref=vdd; fs=44.1khz; bick=64fs; signal frequency=1khz; 18bit input data; measurement frequency=10hz ~ 20khz; r l 3 10k w ; unless otherwise specified) parameter min typ max units dynamic characteristics (note 3) thd+n (0db output) -83 -74 db dynamic range (-60db output, a-weight) 88 94 db s/n (a-weight) 88 94 db interchannel isolation 90 100 db dc accuracy interchannel gain mismatch 0.1 0.5 db gain drift - 60 - ppm/ c output voltage (note 4) 1.02 1.10 1.18 vpp load resistance 10 k w power supplies power supply current normal operation ( pd = h) vdd power-down mode ( pd = l) vdd (note 5) 3.0 10 4.7 50 ma m a power dissipation (vdd) normal operation power-down mode (note 5) 6.0 20 9.4 100 mw m w power supply rejection - 50 - db note 3. measured by ad725c (shibasoku). averaging mode. in case of vdd=3.0v, thd+n: -89db dr: 96db (a-weight) s/n: 97db (a-weight) note 4. full-scale voltage (0db). output voltage scales with the voltage of vref. aout (typ.@0db)=1.10vpp*vref/2. note 5. in case of power-down mode, all digital input pins including clock pins (mclk,bick and lrck) are held vdd or vss. www.datasheet.co.kr datasheet pdf - http://www..net/
asahi kasei [ak4352] m0040-e-02 2000/11 - 5 - filter characteristics (ta=25 c; vdd=1.8 ~ 3.6v; fs=44.1khz; dem= l) parameter symbol min typ max units digital filter passband -0.1db (note 6) -6.0db pb 0 - 22.05 20.0 - khz khz stopband (note 6) sb 24.1 khz passband ripple pr 0.06 db stopband attenuation sa 43 db group delay (note 7) gd - 14.7 - 1/fs digital filter + analog filter frequency response 0 ~ 20.0khz - 0.2 -db note 6. the passband and stopband frequencies scale with fs. for example, pb=0.4535*fs(@-0.1db), sb=0.546*fs(@-43db). note 7. the calculating delay time which occurred by digital filtering. this time is from setting the 18bit data of both channels to input register to the output of analog signal. digital characteristics (ta=25 c; vdd=1.8 ~ 3.6v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 75 % vdd - - - - 25 % vdd v v input leakage current iin - - 10 m a www.datasheet.co.kr datasheet pdf - http://www..net/
asahi kasei [ak4352] m0040-e-02 2000/11 - 6 - switching characteristics (ta=25 c; vdd=1.8 ~ 3.6v) parameter symbol min typ max units master clock timing 256fs: pulse width low pulse width high 384fs: pulse width low pulse width high fclk tclkl tclkh fclk tclkl tclkh 2.048 28 28 3.072 23 23 11.2896 16.9344 12.8 19.2 mhz ns ns mhz ns ns lrck frequency fs 8 44.1 50 khz serial interface timing (note 8) bick period bick pulse width low pulse width high bick rising to lrck edge (note 9) lrck edge to bick rising (note 9) sdata hold time sdata setup time tbck tbckl tbckh tblr tlrb tsdh tsds 312.5 100 100 50 50 50 50 ns ns ns ns ns ns ns reset timing pd pulse width (note 10) trst 300 ns note 8. refer to the operating overview section audio data interface. note 9. bick rising edge must not occur at the same time as lrck edge. note 10. the ak4352 can be reset by bringing pd = l to h only upon power up. n timing diagram lrck bick tblr tlrb tbckl tbckh 50% vdd 50% vdd sdata 50% vdd tsdh tsds lsb audio data input timing trst 25%vdd pd reset timing www.datasheet.co.kr datasheet pdf - http://www..net/
asahi kasei [ak4352] m0040-e-02 2000/11 - 7 - operation overview n system clock the external clocks which are required to operate the ak4352 are mclk (256fs/384fs) lrck (fs), bick (32fs ~ ). the master clock (mclk) should be synchronized with lrck but the phase is not critical. the frequency of mclk is determined by the sampling rate (lrck) and cks pin. setting cks= l selects an mclk frequency of 256fs while setting cks= h selects 384fs. when the 384fs is selected, the internal master clock becomes 256fs(=384fs*2/3). table 1 illustrates standard audio word rates and corresponding frequencies used in the ak4352. all external clocks (mclk, bick and lrck) should always be present whenever the ak4352 is in normal operation mode ( pd = h). if these clocks are not provided, the ak4352 may draw excess current because the device utilizes dynamic refreshed logic internally. if the external clocks are not present, the ak4352 should be in the power-down mode( pd = l). as the ak4352 includes the phase detection circuit for lrck, the ak4352 adjusts the phase of lrck automatically when the synchronization is out of phase by changing the clock frequencies. therefore, the reset is only needed for power-up. mclk lrck (fs) cks= l: 256fs cks= h: 384fs bick (64fs) 32.0khz 8.1920mhz 12.2880mhz 2.0480mhz 44.1khz 11.2896mhz 16.9344mhz 2.8224mhz 48.0khz 12.2880mhz 18.4320mhz 3.0720mhz table 1. examples of system clock mclk 2/3 cks 256fs h l 256fs or 384fs figure 1. internal clock circuit www.datasheet.co.kr datasheet pdf - http://www..net/
asahi kasei [ak4352] m0040-e-02 2000/11 - 8 - n audio serial interface format the ak4352 interfaces with external system by using sdata, bick and lrck pins. four types of data format are available and one of them is selected by setting dif0 and dif1. format 0 is compatible with existing 16bit dacs and digital filters. format 1 is an 18bit version of format 0. format 2 is similar to akm adcs and many dsp serial ports. format 3 is compatible with the i 2 s serial data protocol. in format 2 and 3, 16bit data followed by two zeros also could be input. in all modes, the serial data is msb first and 2s complement format. dif1 dif0 mode bick figure 0 0 0: 16bit lsb justified 3 32fs figure 2 0 1 1: 18bit lsb justified 3 36fs figure 2 1 0 2: 18bit msb justified 3 36fs figure 3 1 1 3: i 2 s compatible 3 32fs or 36fs figure 4 table 2. digital input formats lrck bick sdata mode 0 sdata mode 1 15:msb, 0:lsb (@16bit data) 15 14 0 dont care dont care 15 14 0 17 16 15 14 0 17 16 17:msb, 0:lsb (@18bit data) dont care dont care rch lch 15 14 0 *mode 1: bick needs 36fs or more than 36fs. figure 2. mode 0,1 timing lrck bick sdata sdata 16bit 18bit 16 17 16 3 2 17 1 0 dont 14 1 0 15 14 15 lch rch care dont care 16 3 2 17 1 0 14 1 0 15 dont care dont care * bick needs 36fs or more than 36fs. figure 3. mode 2 timing www.datasheet.co.kr datasheet pdf - http://www..net/
asahi kasei [ak4352] m0040-e-02 2000/11 - 9 - lch rch 15 14 1 0 15 17 16 32 17 10 lrck bick sdata 16bit sdata 18bit dont care dont care 16 32 17 10 15 14 1 0 dont care dont care * bick needs 32fs or 36fs or more than 36fs. figure 4. mode 3 timing n de-emphasis filter the ak4352 includes the digital de-emphasis filter (tc=50/15 m s) by iir filter. this filter corresponds to 44.1khz sampling. the de-emphasis is enabled by setting dem pin h. n power-down the ak4352 is placed in the power-down mode by bringing pd pin l and the anlog outputs are floating(hi-z). figure 5 shows an example of the system timing at the power-down and power-up. normal operation internal state pd power-down normal operation gd gd 0data d/a out (analog) d/a in (digital) clock in mclk,lrck,bick (1) (2) (4) external mute (5) (1) (3) (3) mute on figure 5. power-down/up sequence example notes: (1) analog output corresponding to digital input have the group delay (gd). (2) analog outputs are floating(hi-z) at the power-down mode. (3) click noise occures at the edges( - ) of the falling edge of pd signal. (4) when the external clocks(mclk,bick,lrck) are stopped, the ak4352 should be in the power-down mode. (5) please mute the analog output externally if the click noise(3) influences system application. the timing example is shown in this figure. www.datasheet.co.kr datasheet pdf - http://www..net/
asahi kasei [ak4352] m0040-e-02 2000/11 - 10 - n system reset the ak4352 should be reset once by bringing pd = l upon power-up. the internal timing starts clocking by lrck - upon exiting reset. system design figure 6 shows the system connection diagram. an evaluation board [akd4352] is available in order to allow an easy study on the layout of a surrounding circuit. mclk 1 pd 2 bick 3 sdata 4 5 dif0 6 dif1 7 dem 8 cks 16 vcml 15 aoutl 14 aoutr 13 vcmr 12 vref 11 vdd 10 vss 9 mode reset + analog 2v system ground analog ground ak4352 top view lch out rch out + + lrck 10 m 0.1 m external clock settin g audio data processor 10 m 10 m + + figure 6. typical connection diagram notes: - lrck = fs, bick 3 32fs or 36fs, mclk = 256fs/384fs. - when aout drives some capacitive load, some resistor should be added in series between aout and capacitive load. www.datasheet.co.kr datasheet pdf - http://www..net/
asahi kasei [ak4352] m0040-e-02 2000/11 - 11 - 1. grounding and power supply decoupling figure 6 shows the power supply connection example. vdd is supplied from analog supply in system. decoupling capacitors for high frequency should be as near to the ak4352 device as possible, with the low value ceramic capacitor between vref and vss being the nearest. 2. voltage reference the differential voltage between vref and vss sets the analog output range. vref pin is normally connected to vdd. an electrolytic capacitor 10 m f parallel with a 0.1 m f ceramic capacitor are attached between vref and vss pins. vcml and vcmr pins are a signal ground of this chip. an electrolytic capacitor less than 10 m f parallel with a 0.1 m f ceramic capacitor attached between vcml, vcmr pins and vss eliminates the effects of high frequency noise. especially, the ceramic capacitor should be connected to these pins as near as possible. no load current may be drawn from vcml and vcmr pins. all signals, especially clocks, should be kept away from the vref, vcml and vcmr pins in order to avoid unwanted coupling into the ak4352. 3. analog outputs the analog outputs are single-ended and centered around the vcml, vcmr voltage. the output signal range is typically 1.10vpp. if the noise generated by the delta-sigma modulator beyond the audio band would be the problem, the attenuation by external filter is required. the output voltage is a positive full scale for 7fffh(@16bit) and a negative full scale for 8000h(@16bit). the ideal output is vcml, vcmr voltage for 0000h(@16bit). dc offsets on analog outputs are eliminated by ac coupling since analog outputs have dc offsets of vcml, vcmr voltage + a few mv. www.datasheet.co.kr datasheet pdf - http://www..net/
asahi kasei [ak4352] m0040-e-02 2000/11 - 12 - package 1.0 0.1 0.1 0 -10 detail a seating plane note: dimension "*" does not include mold flash. | 0.10 0.17 0.05 0.22 0.1 0.65 *5.0 1.10max a 1 8 9 16 16pin tssop ( unit: mm ) *4.4 6.4 0.2 0.5 0.2 n package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder plate www.datasheet.co.kr datasheet pdf - http://www..net/
asahi kasei [ak4352] m0040-e-02 2000/11 - 13 - marking akm 4352vt xxyyy contents of xxyyy xx: lot# yyy: date code important notice these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: a. a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification. www.datasheet.co.kr datasheet pdf - http://www..net/

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